Micro-credential Verification of Digital and Mixed-Signal Chips

This course is aimed at students with a Master of Electronics and ICT Engineering Technology, a Master of Engineering: Computer Science or professional bachelors with relevant work experience.
Prior knowledge on following topics is necessary: basics of digital circuits, understanding of, and experience with, any hardware description language (VHDL, Verilog or SystemVerilog).
A solid understanding of the English language is required.

Electronic chips, or integrated circuits are everywhere. They are essential for a wide range of daily-use products, from your credit card to your smartphones. From your dishwasher to your car. Chips are everywhere! The pandemic has revealed the strategic importance of chips. A shortage of chips leads to economic slow-down and chip-supply dependencies lead to geo-political tensions. However, shortage of technical skilled people that know how to design and develop a chip is a much bigger problem. A broad offer of training courses for reskilling and upskilling the workforce in this field is essential.
In this course, instructors from KU Leuven and multiple companies in the chip industry, will introduce students to the why and what of the digital chip design flow and will learn them all about digital and mixed-signal simulation and verification. The course offers theoretical sessions as well as hands-on training.

LEARNING OBJECTIVES
Upon completion of this course, the student:
• has insight in the close relationship between design and verification for digital logic and systems on a chip,
• has insight in the multiple methods to assist in verifying the functionality of a given digital design: Linting / Code Review; Clock Domain Crossing (CDC); RTL / Netlist Simulation; Emulation; Formal Property Verification (FPV),
• has insight in multiple industry standard methods to make a given design more robust and help avoid or eliminate edge-cases when taking the digital design through the full ASIC development pipeline: Formal Verification; Static Timing Analysis (STA); Back-end checks: Cross talk, IR drop, Layout vs Schematic (LVS), Design rule checks,
• has insight in multiple approaches for testbenches: visual verification (checking the waves); golden reference files, Compare with model; combine with inverse model (eg. TX - RX); direct testing vs randomization; assertion based verification; code coverage, functional coverage, cover points; interpreting the results of a testbench and debugging the design,
• has insight in and can create, implement and modify a UVM testbench,
• has insight in simulating Analog-Mixed Signal designs: how the simulators work, with regard to an analog vs digital solver; requirements management and test runs; development of a mixed signal chip, from concept to tapeout,
• has insight in the design and verification of a System on chip design: verification of software in an SoC; using different layers of abstraction by means of behavioural modelling,
• can utilize the learning content during the hands-on workshops.

PROGRAMME
• Introduction to digital chip design flow
• Functional and toolflow verification
• Simulation testbench styles and strategies
• Simulation platforms
• Mixed signal verification

The full programme can be found at https://www.esat.kuleuven.be/mc_chips/courses/digital-and-mixed-signal-simulation-verification(opent in nieuw venster)